Cypress Computer Hardware CY62158EV30 User Manual

CY62158EV30 MoBL®  
8-Mbit (1024K x 8) Static RAM  
Features  
Functional Description [2]  
• Very high speed: 45 ns  
The CY62158EV30 is a high performance CMOS static RAM  
organized as 1024K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current.  
— Wide voltage range: 2.20V–3.60V  
• Pin compatible with CY62158DV30  
• Ultra low standby power  
®
This is ideal for providing More Battery Life™ (MoBL ) in  
portable applications such as cellular telephones. The device  
also has an automatic power down feature that significantly  
reduces power consumption. Placing the device into standby  
mode reduces power consumption significantly when  
deselected (CE HIGH or CE LOW). The eight input and  
— Typical standby current: 2 µA  
— Maximum standby current: 8 µA  
• Ultra low active power  
1
2
output pins (IO through IO ) are placed in a high impedance  
0
7
— Typical active current: 1.8 mA @ f = 1 MHz  
• Easy memory expansion with CE , CE , and OE features  
state when the device is deselected (CE HIGH or CE LOW),  
1
2
the outputs are disabled (OE HIGH), or a write operation is in  
progress (CE LOW and CE HIGH and WE LOW).  
1
2
• Automatic power down when deselected  
• CMOS for optimum speed/power  
1
2
To write to the device, take Chip Enables (CE LOW and CE  
1
2
HIGH) and Write Enable (WE) input LOW. Data on the eight  
• Offered in Pb-free 48-ball VFBGA, 44-pin TSOP II and  
48-pin TSOP I packages  
IO pins (IO through IO ) is then written into the location  
0
7
specified on the address pins (A through A ).  
0
19  
To read from the device, take Chip Enables (CE LOW and  
1
CE HIGH) and OE LOW while forcing the WE HIGH. Under  
2
these conditions, the contents of the memory location  
specified by the address pins appear on the IO pins. See the  
“Truth Table” on page 8 for a complete description of read and  
write modes.  
Logic Block Diagram  
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
IO  
0
DATA IN DRIVERS  
IO  
1
IO  
2
1024K x 8  
ARRAY  
IO  
3
IO  
IO  
IO  
IO  
4
5
6
7
A
A
A
A
9
10  
11  
12  
CE  
CE  
1
2
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Notes  
1. For 48 pin TSOP I pin configuration and ordering information, please refer to CY62157EV30 Data sheet.  
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05578 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised April 19, 2007  
 
   
CY62158EV30 MoBL®  
Output Current into Outputs (LOW)............................. 20 mA  
Maximum Ratings  
Static Discharge Voltage............................................>2001V  
(MIL-STD-883, Method 3015)  
Exceeding the maximum ratings may impair the useful life of  
the device. These user guidelines are not tested.  
Latch up Current......................................................>200 mA  
Storage Temperature ..................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Ambient  
Supply Voltage to Ground Potential0.3V to V  
+ 0.3V  
Product  
Range  
Temperature  
V
CC  
CC(max)  
(T )  
A
DC Voltage Applied to Outputs  
CY62158EV30LL Industrial –40°C to +85°C 2.2V – 3.6V  
in High-Z State  
......................... –0.3V to V  
+ 0.3V  
+ 0.3V  
CC(max)  
..................... –0.3V to V  
CC(max)  
DC Input Voltage  
Electrical Characteristics (Over the Operating Range)  
45 ns  
Parameter  
Description  
Test Conditions  
= –0.1 mA  
Unit  
Min  
2.0  
2.4  
Typ  
Max  
V
Output HIGH Voltage  
I
I
I
I
V
V
OH  
OL  
IH  
OH  
OH  
OL  
OL  
= –1.0 mA, V > 2.70V  
CC  
V
V
V
I
Output LOW Voltage  
Input HIGH Voltage  
Input LOW Voltage  
= 0.1 mA  
0.4  
0.4  
V
= 2.1 mA, V > 2.70V  
V
CC  
V
V
V
V
= 2.2V to 2.7V  
= 2.7V to 3.6V  
= 2.2V to 2.7V  
= 2.7V to 3.6V  
1.8  
2.2  
V
V
+ 0.3V  
V
CC  
CC  
CC  
CC  
CC  
CC  
+ 0.3V  
0.6  
0.8  
+1  
V
–0.3  
–0.3  
–1  
V
IIL  
V
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
µA  
µA  
mA  
mA  
IX  
I
I
I
GND < V < V , Output Disabled  
–1  
+1  
OZ  
O
CC  
V
OperatingSupplyCurrent f = f  
= 1/t  
V
= V  
CCmax  
= 0 mA  
18  
25  
CC  
CC  
max  
RC  
CC  
I
OUT  
f = 1 MHz  
1.8  
3
CMOS levels  
I
Automatic CE  
Power down Current —  
CMOS Inputs  
CE > V – 0.2V, CE < 0.2V  
2
8
µA  
SB1  
1
CC  
2
V
> V – 0.2V, V < 0.2V)  
IN CC IN  
f = f  
(Address and Data Only),  
max  
f = 0 (OE and WE), V = 3.60V  
CC  
I
Automatic CE  
Power down Current —  
CMOS Inputs  
CE > V – 0.2V or CE < 0.2V,  
2
8
µA  
SB2  
1
CC  
2
V
> V – 0.2V or V < 0.2V,  
IN  
CC  
IN  
f = 0, V = 3.60V  
CC  
Capacitance[9]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
Max  
10  
Unit  
C
C
T = 25°C, f = 1 MHz,  
pF  
pF  
IN  
A
V
= V  
CC  
CC(typ)  
10  
OUT  
Notes  
5.  
6.  
V
V
= –2.0V for pulse durations less than 20 ns.  
IL(min)  
= V + 0.75V for pulse duration less than 20 ns.  
IH(max)  
CC  
7. Full device AC operation assumes a 100 µs ramp time from 0 to V (min) and 200 µs wait time after V stabilization.  
CC  
CC  
8. Only chip enables (CE and CE ) must be at CMOS level to meet the I / I spec. Other inputs can be left floating.  
1
2
SB2 CCDR  
9. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 38-05578 Rev. *D  
Page 3 of 11  
 
         
CY62158EV30 MoBL®  
Thermal Resistance[9]  
Parameter  
Description  
Test Conditions  
BGA  
TSOP II  
Unit  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 x 4.5 inch,  
two-layer printed circuit board  
72  
76.88  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
8.86  
13.52  
°C/W  
JC  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
VCC  
VCC  
90%  
10%  
OUTPUT  
10%  
GND  
R2  
Fall time: 1 V/ns  
30 pF  
Rise Time: 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THÉVENIN EQUIVALENT  
RTH  
VTH  
OUTPUT  
Parameters  
2.5V  
16667  
15385  
8000  
1.20  
3.0V  
1103  
1554  
645  
Unit  
R1  
R2  
V
R
TH  
V
1.75  
TH  
Data Retention Characteristics (Over the Operating Range)  
[4]  
Parameter  
Description  
Conditions  
Min  
Typ  
Max  
Unit  
V
V
I
V
for Data Retention  
1.5  
DR  
CC  
[8]  
Data Retention Current  
V
= 1.5V, CE > V 0.2V  
2
5
µA  
CCDR  
CC  
1
CC  
or CE < 0.2V, V > V 0.2V  
or V < 0.2V  
2
IN  
CC  
IN  
t
t
Chip Deselect to Data  
Retention Time  
0
ns  
ns  
CDR  
Operation Recovery  
Time  
t
RC  
R
Data Retention Waveform  
DATA RETENTION MODE  
V
, min  
V
> 1.5V  
V
V
, min  
CC  
CC  
CC  
DR  
t
t
CDR  
R
CE  
1
or  
CE  
2
Note  
10. Full Device AC operation requires linear V ramp from V to V  
> 100 µs or stable at V  
> 100 µs.  
CC(min)  
CC  
DR  
CC(min)  
Document #: 38-05578 Rev. *D  
Page 4 of 11  
 
   
CY62158EV30 MoBL®  
Switching Characteristics (Over the Operating Range)  
45 ns  
Parameter  
Read Cycle  
Description  
Unit  
Min  
Max  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
45  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
45  
AA  
Data Hold from Address Change  
CE LOW and CE HIGH to Data Valid  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
22  
1
2
OE LOW to Data Valid  
OE LOW to Low Z  
5
10  
0
OE HIGH to High Z  
CE LOW and CE HIGH to Low Z  
18  
18  
45  
1
2
CE HIGH or CE LOW to High Z  
1
2
CE LOW and CE HIGH to Power Up  
1
2
CE HIGH or CE LOW to Power Down  
PD  
1
2
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
CE LOW and CE HIGH to Write End  
45  
35  
35  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
SCE  
AW  
1
2
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
HA  
0
SA  
35  
25  
0
PWE  
SD  
Data Setup to Write End  
Data Hold from Write End  
HD  
WE LOW to High Z  
18  
HZWE  
LZWE  
WE HIGH to Low Z  
10  
Notes  
11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1V/ns), timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in “AC Test Loads and Waveforms” on page 4.  
CC(typ)  
OL OH  
12. At any given temperature and voltage condition, t  
is less than t  
, t  
for any given device.  
LZWE  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
13. t  
, t  
, and t  
transitions are measured when the outputs enter a high impedance state.  
HZOE HZCE  
HZWE  
14. The internal write time of the memory is defined by the overlap of WE, CE = V , and CE = V . All signals must be ACTIVE to initiate a write and any of these  
1
IL  
2
IH  
signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.  
Document #: 38-05578 Rev. *D  
Page 5 of 11  
 
       
CY62158EV30 MoBL®  
Switching Waveforms  
Read Cycle No. 1 (Address Transition Controlled)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
DATA OUT  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
t
RC  
CE  
1
CE  
2
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
VCC  
DATA VALID  
t
LZCE  
t
PD  
ICC  
t
PU  
50%  
SUPPLY  
50%  
ISB  
CURRENT  
Notes  
15. Device is continuously selected. OE, CE = V , CE = V .  
1
IL  
2
IH  
16. WE is HIGH for read cycle.  
17. Address valid before or similar to CE transition LOW and CE transition HIGH.  
1
2
Document #: 38-05578 Rev. *D  
Page 6 of 11  
 
     
CY62158EV30 MoBL®  
Switching Waveforms (continued)  
[14, 18, 19]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
VALID DATA  
DATA IO  
t
HZOE  
Write Cycle No. 2 (CE or CE Controlled)  
1
2
t
WC  
ADDRESS  
t
SCE  
CE  
1
t
SA  
CE  
2
t
t
HA  
AW  
t
PWE  
WE  
OE  
t
t
HD  
SD  
DATA IO  
VALID DATA  
Notes  
18. Data IO is high impedance if OE = V  
.
IH  
19. If CE goes HIGH or CE goes LOW simultaneously with WE HIGH, the output remains in high impedance state.  
1
2
20. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 38-05578 Rev. *D  
Page 7 of 11  
 
     
CY62158EV30 MoBL®  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
t
SCE  
CE  
1
CE  
2
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
VALID DATA  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
X
CE  
WE  
X
OE  
X
Inputs/Outputs  
Mode  
Power  
1
2
X
High Z  
High Z  
Data Out  
High Z  
Data in  
Deselect/Power Down  
Deselect/Power Down  
Read  
Standby (I  
Standby (I  
)
SB  
SB  
L
X
X
)
L
H
H
L
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
L
H
H
H
X
Output Disabled  
Write  
L
H
L
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
45  
CY62158EV30LL-45BVXI 51-85150 48-ball Very Fine Pitch Ball Grid Array (Pb-free)  
CY62158EV30LL-45ZSXI 51-85087 44-pin TSOP II (Pb-free)  
Industrial  
Document #: 38-05578 Rev. *D  
Page 8 of 11  
 
 
CY62158EV30 MoBL®  
Package Diagrams  
Figure 1. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
Ø0.30 0.05(48X)  
A1 CORNER  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85150-*D  
Document #: 38-05578 Rev. *D  
Page 9 of 11  
 
CY62158EV30 MoBL®  
Package Diagrams (continued)  
Figure 2. 44-Pin TSOP II, 51-85087  
51-85087-*A  
MoBL is a registered trademark, and More Battery Life is a trademark of Cypress Semiconductor. All product and company names  
mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05578 Rev. *D  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2004-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the  
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to  
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
 
CY62158EV30 MoBL®  
Document History Page  
®
Document Title: CY62158EV30 MoBL , 8-Mbit (1024K x 8) Static RAM  
Document Number: 38-05578  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
**  
270329  
291271  
See ECN  
See ECN  
PCI  
New Data Sheet  
Converted from Advance Information to Preliminary  
Changed I from 4 to 4.5 µA  
*A  
SYT  
CCDR  
*B  
444306  
See ECN  
NXR  
Converted from Preliminary to Final.  
Removed 35 ns speed bin  
Removed “L” bin.  
Removed 44 pin TSOP II package  
Included 48 pin TSOP I package  
Changed the I Typ value from 16 mA to 18 mA and I max value from 28  
CC  
CC  
mA to 25 mA for test condition f = fax = 1/t  
RC.  
Changed the I max value from 2.3 mA to 3 mA for test condition f = 1MHz.  
CC  
Changed the I  
and I  
max value from 4.5 µA to 8 µA and Typ value from  
SB1  
SB2  
0.9 µA to 2 µA respectively.  
Updated Thermal Resistance table  
Changed Test Load Capacitance from 50 pF to 30 pF.  
Added Typ value for I  
CCDR .  
Changed the I  
max value from 4.5 µA to 5 µA  
CCDR  
Corrected t in Data Retention Characteristics from 100 µs to t ns  
R
RC  
Changed t  
Changed t  
Changed t  
Changed t  
from 3 to 5  
from 6 to 10  
from 22 to 18  
from 30 to 35  
LZOE  
LZCE  
HZCE  
PWE  
Changed t from 22 to 25  
SD  
Changed t  
from 6 to 10  
LZWE  
Updated the ordering Information and replaced the Package Name column with  
Package Diagram.  
*C  
*D  
467052  
See ECN  
See ECN  
NXR  
VKN  
Included 44 pin TSOP II package in Product Offering.  
Removed TSOP I package; Added reference to CY62157EV30 TSOP I  
Updated the ordering Information table  
1015643  
Added footnote #8 related to I  
and I  
SB2 CCDR  
Document #: 38-05578 Rev. *D  
Page 11 of 11  
 

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